`timescale 1ns / 100ps

module MainCode_tb;

	reg				CLK_50MHz;
	reg				CLK_100Hz_test;
	reg				CLK_1Hz_test;
	reg				rst_n;
	reg				start_stop;
	reg				mode_sel;

	wire	[6:0]	HexMSBH;
	wire	[6:0]	HexMSBL;
	wire	[6:0]	HexLSBH;
	wire	[6:0]	HexLSBL;
	wire			DOT;
	wire	[9:0]	LED;

	MainCode dut (
		.CLK_50MHz(CLK_50MHz),
		.CLK_100Hz_test(CLK_100Hz_test),
		.CLK_1Hz_test(CLK_1Hz_test),
		.rst_n(rst_n),
		.StartStop(start_stop),
		.ModeSel(mode_sel),
		.HexMSBH(HexMSBH),
		.HexMSBL(HexMSBL),
		.HexLSBH(HexLSBH),
		.HexLSBL(HexLSBL),
		.DOT(DOT),
		.LED(LED)
	);

	initial begin
		CLK_50MHz = 0;
		CLK_100Hz_test = 0;
		CLK_1Hz_test = 0;
	end

	always #10    CLK_50MHz     = ~CLK_50MHz;
	always #50    CLK_100Hz_test = ~CLK_100Hz_test;
	always #5000  CLK_1Hz_test   = ~CLK_1Hz_test;

	initial begin
		rst_n = 0;
		start_stop = 1;
		mode_sel = 1;

		#100;
		rst_n = 1;

		#100;
		start_stop = 0;
		#500;
		start_stop = 1;

		#130000;

		start_stop = 0;
		#500;
		start_stop = 1;
		#10000

		rst_n = 0;
		#100;
		rst_n = 1;

		#100;
		start_stop = 0;
		#500;
		start_stop = 1;

		#500000;

		mode_sel = 0;
		#10 start_stop = 0;
		#20;
		start_stop = 1;

		#200000;

		#10 start_stop = 0;
		#20;
		start_stop = 1;

		#1000000;

		$stop;
	end

endmodule

